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spice mos transistor saturation
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bill_jetson321@yahoo.com
electronics forum beginner


Joined: 18 Jul 2006
Posts: 1

PostPosted: Tue Jul 18, 2006 9:42 pm    Post subject: spice mos transistor saturation Reply with quote

Hi,

I've been trying some analog IC design but I'm running into difficulty
with things conceptually ("seeing" what is going on in the circuit) and
practically (getting something I've made to work, in simulation) - ie.
moving beyond what I was taught at university.

Specifically for the latter, I keep running into problems with getting
FETs to run in saturation. For example, an NMOS cascoded current
mirror: I've got the two cascoded input transistors on the left with
drain and gate connected, so no matter what, these will always be in
saturation. Then, connecting the gates of these biasing transistors to
the gates of two cascoded output transistors, with the same Vgs, the
output transistors should operate with the same drain current. But I've
got an active PMOS load above the current mirror and it is dropping
about 2.4V (with 2.5V supply rails), leaving only a few mV across the
drain-source of the cascoded output transistors, so that they operate
in their linear region instead of in saturation. The input transistors
have an almost identical load as the output, but as they have their
gate and drain tied together, they do stay in saturation.

So I guess my question is: how do I go about stopping the PMOS load
dropping all my voltage? The PMOS and NMOS transistors have W/L ratios
such that the PMOS is 1.5 times the NMOS, but changing these ratios
doesn't seem to have a significant effect on the output NMOS Vds.

Thanks for any enlightenment!

Bill
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Jim Thompson
electronics forum Guru


Joined: 06 May 2005
Posts: 5440

PostPosted: Tue Jul 18, 2006 10:46 pm    Post subject: Re: spice mos transistor saturation Reply with quote

On 18 Jul 2006 14:42:55 -0700, bill_jetson321@yahoo.com wrote:

Quote:
Hi,

I've been trying some analog IC design but I'm running into difficulty
with things conceptually ("seeing" what is going on in the circuit) and
practically (getting something I've made to work, in simulation) - ie.
moving beyond what I was taught at university.

Specifically for the latter, I keep running into problems with getting
FETs to run in saturation. For example, an NMOS cascoded current
mirror: I've got the two cascoded input transistors on the left with
drain and gate connected, so no matter what, these will always be in
saturation. Then, connecting the gates of these biasing transistors to
the gates of two cascoded output transistors, with the same Vgs, the
output transistors should operate with the same drain current. But I've
got an active PMOS load above the current mirror and it is dropping
about 2.4V (with 2.5V supply rails), leaving only a few mV across the
drain-source of the cascoded output transistors, so that they operate
in their linear region instead of in saturation. The input transistors
have an almost identical load as the output, but as they have their
gate and drain tied together, they do stay in saturation.

So I guess my question is: how do I go about stopping the PMOS load
dropping all my voltage? The PMOS and NMOS transistors have W/L ratios
such that the PMOS is 1.5 times the NMOS, but changing these ratios
doesn't seem to have a significant effect on the output NMOS Vds.

Thanks for any enlightenment!

Bill

I suspect you have a current source loaded by a current sink??

Think about it... it doesn't have a stable operating point unless
there's some sort of feedback loop.

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice:(480)460-2350 | |
| E-mail Address at Website Fax:(480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.
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Chris Jones
electronics forum Guru Wannabe


Joined: 06 May 2005
Posts: 278

PostPosted: Tue Jul 18, 2006 11:44 pm    Post subject: Re: spice mos transistor saturation Reply with quote

bill_jetson321@yahoo.com wrote:

Quote:
Hi,

I've been trying some analog IC design but I'm running into difficulty
with things conceptually ("seeing" what is going on in the circuit) and
practically (getting something I've made to work, in simulation) - ie.
moving beyond what I was taught at university.

Specifically for the latter, I keep running into problems with getting
FETs to run in saturation. For example, an NMOS cascoded current
mirror: I've got the two cascoded input transistors on the left with
drain and gate connected, so no matter what, these will always be in
saturation. Then, connecting the gates of these biasing transistors to
the gates of two cascoded output transistors, with the same Vgs, the
output transistors should operate with the same drain current. But I've
got an active PMOS load above the current mirror and it is dropping
about 2.4V (with 2.5V supply rails), leaving only a few mV across the
drain-source of the cascoded output transistors, so that they operate
in their linear region instead of in saturation. The input transistors
have an almost identical load as the output, but as they have their
gate and drain tied together, they do stay in saturation.

So I guess my question is: how do I go about stopping the PMOS load
dropping all my voltage? The PMOS and NMOS transistors have W/L ratios
such that the PMOS is 1.5 times the NMOS, but changing these ratios
doesn't seem to have a significant effect on the output NMOS Vds.

Thanks for any enlightenment!

Bill

A diagram would be helpful, (in particular the PMOS "active load" that you
mention). If you can put a diagram on a website or ABSE, then that would
be good.

Chris
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Joerg
electronics forum Guru


Joined: 05 May 2005
Posts: 3533

PostPosted: Wed Jul 19, 2006 12:11 am    Post subject: Re: spice mos transistor saturation Reply with quote

Hello Bill,

Quote:

I've been trying some analog IC design but I'm running into difficulty
with things conceptually ("seeing" what is going on in the circuit) and
practically (getting something I've made to work, in simulation) - ie.
moving beyond what I was taught at university.

Specifically for the latter, I keep running into problems with getting
FETs to run in saturation. For example, an NMOS cascoded current
mirror: I've got the two cascoded input transistors on the left with
drain and gate connected, so no matter what, these will always be in
saturation. Then, connecting the gates of these biasing transistors to
the gates of two cascoded output transistors, with the same Vgs, the
output transistors should operate with the same drain current. But I've
got an active PMOS load above the current mirror and it is dropping
about 2.4V (with 2.5V supply rails), leaving only a few mV across the
drain-source of the cascoded output transistors, so that they operate
in their linear region instead of in saturation. The input transistors
have an almost identical load as the output, but as they have their
gate and drain tied together, they do stay in saturation.

So I guess my question is: how do I go about stopping the PMOS load
dropping all my voltage? The PMOS and NMOS transistors have W/L ratios
such that the PMOS is 1.5 times the NMOS, but changing these ratios
doesn't seem to have a significant effect on the output NMOS Vds.


I am not a chip design expert like Jim but how is that PMOS load biased?

As Chris mentioned a circuit diagram will greatly help here.

--
Regards, Joerg

http://www.analogconsultants.com
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